1. Field of the Invention
The present invention relates to an inverter control unit that controls active power and/or reactive power.
2. Description of the Related Art
FIG. 4 shows a step-down transformer referred to as a "receiving transformer" and an inverter unit referred to as an "active filter", in Mitsubishi Electric Technical Report, Vol. 65, No. 6, 1991, "Arc Furnace Flicker Compensating Large-Capacitance Active Filter", p. 62 (582). FIG. 4 is a single phase wiring diagram showing FIG. 6 of the referenced publication without a higher harmonic filter and an arc furnace load.
In FIG. 4, reference numeral 5 denotes an invertor unit; 1, an a.c.-d.c. transformer of the inverter unit 5; 2, an inverter transformer of the inverter unit 5; 4, a system voltage source; and 3, a step-down transformer with a variable tap which links the inverter unit 1 to the system voltage source 4. The tap of the step-down transformer 3 is variably controlled by a control circuit 10. Reference numeral 6 denotes a d.c. capacitor of the inverter unit 5.
Reference numeral 7 denotes a d.c. energy unit connected to a d.c. side of the inverter unit 7 that supplies or consumes power to the inverter unit 5. The d.c. energy unit 7 is designed, for example, as follows:
a) a d.c. capacitor circuit; PA1 b) a d.c. circuit connected directly to a d.c. energy storage means such as a battery; PA1 c) a d.c. circuit connected indirectly to a d.c. energy storage means such as a battery, a chopper circuit and so on, and whose d.c. voltage is controlled to be constant; PA1 d) a d.c. circuit that can be charged from an external power supply; PA1 e) a d.c. circuit that can be discharged by a resistor or the like; PA1 f) a d.c. circuit of an inverter unit whose a.c. side is connected to a power generator or the like; PA1 g) a d.c. circuit of an inverter unit whose a.c. side is connected to an electric motor having an energy storage means such as a flywheel; and PA1 h) a transformer and a rectifier circuit having a an AVR (automatic voltage regulation) function.
FIG. 5 shows an example of the control circuit 10 that actuates the variable tap of the step-down transformer 3 with the variable tap.
In FIG. 5, reference numeral 11 denotes an effective value calculating circuit that calculates the effective value of a system voltage V.sub.0 ; 12, a setting circuit for setting an effective value command value V.sub.0 * of the system voltage V.sub.0 ; 13, a deviation calculating circuit for calculating a deviation .DELTA. V.sub.0 between the effective value and a command value V.sub.0 * of the system voltage V.sub.0 ; 14, a tap command circuit for instructing a change in tap position corresponding to the system voltage deviation .DELTA. V.sub. ; and 18, a tap changing circuit for comparing an output of the tap command circuit 14 with a current tap to change the tap position of the step-down transformer 3 with a time delay element.
Then, the operation will be described.
The system voltage V.sub.0 steadily goes up or down, for example, 5% of a rated voltage V.sub.0, according to the operating state of a load connected to the system voltage source 4. In this state, a deviation between an output value from the effective value calculating circuit 11 for the system voltage V.sub.0 and the effective value command value V.sub.0 * from the setting circuit 12 is calculated by the deviation calculating circuit 13. A tap position corresponding to the system voltage deviation .DELTA. V.sub.0 is commanded from the tap command circuit 14, and the tap command value outputted from the tap command circuit 14 is compared with the current tap position for changing the tap with the time delay by the tap changing circuit 18. As a result, the step-down transformer 3 with a variable tap changes the voltage tap position with a load connected so that a secondary voltage V.sub.s is restrained to within a tap width .DELTA. V.sub.s.
FIG. 6 shows a single phase wiring diagram of the step-down transformer 3 with a variable tap for one phase.
When the system voltage V.sub.0 is equal to rated voltage, the variable tap produces a tap voltage V.sub.k shown in FIG. 6, but when the system voltage V.sub.0 steadily goes up and is higher than a rated value, the variable tap is gradually moved toward V.sub.1 shown in FIG. 6, step by step, in predetermined time intervals, and is controlled in such a manner that a secondary voltage V.sub.s is restrained within a given range of the rated voltage.
On the other hand, when the system voltage V.sub.0 steadily goes down and is lower than the rated value, the variable tap is gradually moved toward V.sub.2 shown in FIG. 6 step by step, in predetermined time intervals, and is controlled in such a manner that the secondary voltage V.sub.s is restrained within a given range of the rated voltage.
The a.c.-d.c. convertor 1 of the inverter unit 5 variably controls the fundamental wave voltage magnitude and the phase of an inverter voltage V.sub.a inputted through the inverter transformer 2 with respect to the fundamental wave voltage magnitude and the phase of the secondary voltage V.sub.s of the step-down transformer 3 with a variable tap. For facilitation of description, it is assumed that the winding ratio of the inverter transformer 2 is set to 1:1, and the magnitude of the secondary voltage V.sub.s is equal to the magnitude of the inverter voltage V.sub.a when the inverter current I.sub.a inputted through the invertor transformer 2 is zero.
Since a difference voltage magnitude .DELTA. V.sub.xa =V.sub.a -V.sub.s of the inverter voltage magnitude V.sub.a and the secondary voltage magnitude V.sub.s is applied to the inverter transformer 2 having an inductance X.sub.a, an magnitude I.sub.a inverter is obtained by dividing the difference inverter current value .DELTA. V.sub.xa by the inductance X.sub.a is generated. In this situation, the phase of the inverter current I.sub.a is delayed with respect to the difference voltage, .DELTA. V.sub.xa, by 90 degrees.
The magnitude and the phase of the inverter voltage V.sub.a generated by the inverter unit 5 is variably controlled according to a direction along which the active power and/or the reactive power flows. When the difference voltage .DELTA. V.sub.xa is identical in phase with the secondary voltage V.sub.s, the inverter voltage V.sub.a increases in magnitud by (V.sub.s +.DELTA.V.sub.xa), and the inverter current I.sub.a is advnaced in phase by 90 degrees from secondary voltage V.sub.s, resulting in a capacitor operation where the phase-advanced reactive power is generated.
When the difference voltage .DELTA. V.sub.xa is shifted in phase from the secondary voltage V.sub.s by about 180 degrees, the inverter voltage V.sub.a decreases in magnitude by (V.sub.s -.DELTA. V.sub.xa), and the inverter current Ia is delayed in phase by 90 degrees from the secondary voltage V.sub.s, resulting in a reactor operation where phase-delayed reactive power is generated.
Also, when the difference voltage .DELTA. V.sub.xa is generated so that the inverter current Ia is in phase with the secondary voltage V.sub.s, the inverter voltage V.sub.a becomes .sqroot.(V.sub.s.sup.2 +.DELTA. V.sub.xa.sup.2), resulting in a converter operation where active power flows from the invertor unit 5.
When the difference voltage .DELTA. V.sub.xa is generated so that the invertor current I.sub.a is different in phase from the secondary voltage V.sub.s by about 180 degrees, the inverter voltage V.sub.a becomes .sqroot.(V.sub.s.sup.2 +.DELTA. V.sub.xa.sup.2), resulting in an inverter operation where active power flows from the invertor unit 5.
The inverter rated voltage V.sub.a0 is defined as the inverter voltage V.sub.a when the inverter current I.sub.a is zero, and the capacitance of the inverter is defined by a product of the inverter current I.sub.a and the inverter rated voltage V.sub.a0.
The relational expression (1) of the d.c. voltage E.sub.d and the inverter rated voltage V.sub.a0 of the inverter unit 5 is as follows: EQU E.sub.d .gtoreq.K.times..sqroot.2.times.V.sub.a0 .times..sqroot.((1+X.sub.a .multidot.I.sub.a .multidot.cos .theta.).sup.2 +(X.sub.a .multidot.I.sub.a .multidot.sin .theta.).sup.2) (1)
where sin .theta.=i.sub.p/.sqroot.(i.sub.p.sup.2 +i.sub.q.sup.2), cos .theta.=i.sub.q/.sqroot.(i.sub.p.sup.2 +i.sub.q.sup.2), and I.sub.a =.sqroot.(i.sub.p.sup.2 +i.sub.q.sup.2) are defined; .theta.=0.degree. is the convertor operation, .theta.=90.degree. is the capacitor operation, .theta.=180.degree. is the inverter operation, and .theta.=270.degree. is the reactor operation; and i.sub.p (&gt;0) is the current of the converter operation, i.sub.q (&gt;0) is the phase-advanced reactive current of the capacitor operation, i.sub.p (&lt;0) is the current of the inverter operation, and i.sub.q (&lt;0) is the reactive current of the reactor operation.
Also, a constant K is a constant determined by the structure or the control performance of the inverter unit 5. K&gt;1 is normally satisfied, for example, K=1.2, but since it is a constant irrelevant to the subject matter of the present invention, K=1, which is an ideal state, is assumed.
Of the capacitor operation, the reactor operation, the converter operation and the inverter operation by the inverter unit 5, the inverter voltage magnitude Va or a peak value (.sqroot.2.times.V.sub.a) becomes maximum during the capacitor operation.
At the time of the capacitor operation, from the relational expression (1) when .theta.=90.degree., the following expression is satisfied. EQU E.sub.d .gtoreq..sqroot.2.times.V.sub.a0 .times.(1+X.sub.a .multidot.I.sub.q) (2)
If an upper limit I.sub.q1 of the generatable phase-advanced reactive current I.sub.q is a controllable maximum current or less of a power semiconductor device (hereinafter referred to as "device"), such as GTO or IGBT as a conversion element of the a.c.-d.c. converter 1, the following expression is satisfied. EQU I.sub.q1 =(E.sub.d /(.sqroot.2.times.V.sub.a0)-1)/X.sub.a (3)
At the time of the converter operation or the inverter operation, the following expression is satisfied from the expression (1) at .theta.=0.degree. or 180.degree.. EQU E.sub.d .gtoreq..sqroot.2.times.V.sub.a0 .times..sqroot.(1+(X.sub.a .multidot.I.sub.p).sup.2) (4)
If an upper limit I.sub.p1 of the generatable effective current I.sub.p is a controllable maximum current or less of the device, the following expression is satisfied. EQU I.sub.p1 =(.sqroot.((E.sub.d /(.sqroot.2.times.V.sub.a0)).sup.2 -1))/X.sub.a(5)
The d.c. voltage E.sub.d of the inverter unit 5 is a constant determined by a device rated voltage or the structure of the inverter unit 5 such as the number of series connections. In the case where the inverter voltage peak value (.sqroot.2.times.V.sub.a0) is designed to be a value having no margin with respect to the inverter d.c. voltage E.sub.d, for example, in case of E.sub.d /(.sqroot.2.times.V.sub.a0)=1.1,X.sub.a=0.2, the magnitude .vertline.i.sub.q1 .vertline. of the phase-advanced reactive current cannot equal the current magnitude value .vertline.i.sub.p1 .vertline. such that I.sub.p1 =2.3 when I.sub.q1 =0.5.
In the conventional inverter control unit thus structured, since a reactive power higher than the rated reactive power determined in design cannot be obtained, the structure per se of the inverter is required to be enlarged, for example, by increasing the device rated voltage and the number of connected devices to increase the d.c. voltage.
Also, there arises a problem that an active power higher than the rated effective power determined in design cannot be obtained, etc.